IEOR - Designing a More Efficient World

2020 Campus—Digital IP Verification Engineer at Synopsys

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Employer: Synopsys

Expires: 07/01/2020

Job Title:2020 Campus-Digital IP Verification EngineerLocation: ShanghaiResponsibility: This position is for leading edge IP verificationStudy existing UVM test environment and make improvementsDefine verification spec based on standard specificationsWrite and debug test cases to verify RTL design at IP levelCollect and improve code and functional coverageMaintain regression tests and debug test failuresWork with VIP teams for VIP issuesQualification: Be familiar with SystemVerilog, knowledge in UVM is a plusBe fluent in English, both speaking and writingKnowledge in software programming, e.g. C/C++, Python, is a plusKnowledge in any high performance interface technologies, e.g. DDR, PCIe, ethernet, is a plusKnowledge in any chip infrastructure, e.g. RISC, AMBA protocols, is a plusHas strong desire to learn and explore new technologiesDemonstrates good attitude in team work