IEOR - Designing a More Efficient World

2020 Campus-Digital IP Design Engineer at Synopsys

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Employer: Synopsys

Expires: 07/01/2020

Job Title: 2020 Campus-Digital IP Design EngineerLocation: ShanghaiResponsibility: This position is for leading edge IP design.Study standard specifications published by JEDECDefine micro architecture at block level based on IP architectureWork on RTL design based on predefined coding style, SVA is also includedClean RTL check violations in lint, CDC, DFT and synthesisRun block level test to speed up IP verificationWork with verification to debug and fix RTL issuesCheck synthesis timing and improve RTL design if requiredQualification:Be familiar with RTL designBe fluent in English, both speaking and writingKnowledge in software programming, e.g. C/C++, Python, is a plusKnowledge in any high performance interface technologies, e.g. DDR, PCIe, ethernet, is a plusKnowledge in any chip infrastructure, e.g. RISC, AMBA protocols, is a plusHas strong desire to learn and explore new technologiesDemonstrates good attitude in team work